The present application relates to a memory device that includes a memory element having a memory layer which stores a magnetization state of a magnetic material as information and a magnetization pinned layer in which a magnetization direction is pinned. A magnetization direction of the memory layer is changed by supplying current, and the memory device is suitably applied to a nonvolatile memory.
Since information communicating apparatuses, in particular, small-sized apparatuses for personal use such as portable communication terminals have been widely used, further high performance such as higher integration, higher operation speed and lower electric power usage is requested for a memory element, logic element or the like included in such apparatuses.
Specifically, a nonvolatile memory may be a necessary component for highly-functional apparatuses.
As a nonvolatile memory, a semiconductor flash memory, FeRAM (Ferroelectric Random Access Memory) or the like has been used and further research and development have been carried out for higher performance.
Lately, as a nonvolatile memory using a magnetic material, MRAM (Magnetic Random Access Memory) using tunnel magneto-resistance effects has been developed and attracting attention (for example, refer to “J. Nahas et al., IEEE/ISSCC 2004 Visulas Supplement, p. 22”).
MRAM includes regularly-arranged minute memory elements in which information is recorded and wiring such as a word line and a bit line provided to access each of the memory element.
Each magnetic memory element is configured to have a memory layer in which information is recorded as a magnetization direction of a ferromagnetic material.
The magnetic memory element employs a structure using MTJ (Magnetic Tunnel Junction), including the above-described memory layer, a tunnel insulating film (non-magnetic spacer) and a magnetization pinned layer where a magnetization direction is pinned. The magnetization direction of the magnetization pinned layer may be pinned by providing an anti-ferromagnetic layer, for example.
In such structure, a tunnel magneto-resistance effect is caused, in which a resistance value to tunnel current flowing through a tunnel insulating film changes in accordance with an angle between the magnetization direction of the memory layer and the magnetization direction of the magnetization pinned layer. Accordingly, information is written (recorded) using the tunnel magneto-resistance effect. The resistance value becomes maximum when the magnetization direction of the memory layer and the magnetization direction of the magnetization pinned layer are anti-parallel, and becomes minimum when these are parallel.
Information is written (recorded) to the above-described magnetic memory element by controlling a magnetization direction of the memory layer in the magnetic memory element using a combined current magnetic field caused by supplying current to both of a word line and a bit line. Typically, magnetization directions are stored corresponding to information “0” and information “1”, respectively.
Japanese Unexamined Patent Application Publication No. H10-116490, for example, discloses a method using an asteroid characteristic, and U.S. Patent Application Publication No. 2003/0072174, for example, discloses a method using a switching characteristic, in order to record information into the memory element.
On the other hand, in order to read recorded information, the recorded information may be detected by detecting a difference between the magnetization directions of the memory layer as a difference between voltage signals using the tunnel magneto-resistance effect of the magnetic memory element after a memory cell is selected using an element such as a transistor.
MRAM has such an advantage that the information “0” and information “1” are rewritten by inverting the magnetization direction of the memory layer formed of a ferromagnetic material and therefore information can be rewritten at high speed and without a limit of times (>1015 times) as compared with other nonvolatile memories.
However, a comparatively intensive current magnetic field may be required for MRAM in order to rewrite recorded information. Therefore, a certain amount of current (for example, several mA to several tens mA) may need to be applied to address wirings. Thus, power consumption may be large.
Further, MRAM may require address wiring for the writing and address wiring for the reading separately, and therefore it is difficult for a memory cell to be miniaturized.
Furthermore, with a memory element miniaturized, such problems as described below may occur. Accordingly, address wiring becomes thin and it is difficult to apply a sufficient amount of current thereto, and power consumption increases due to the intensive current magnetic field required for large coercive force.
Therefore, it has been difficult to miniaturize the element.
U.S. Pat. No. 5,695,864, for example, discloses a method for coping with such problems, in which recording without using a current magnetic field is studied and, in particular, a memory that uses magnetization inversion based on spin-transfer attracts attention as a configuration in which the magnetization direction can be inverted with less current.
Japanese Unexamined Patent Application Publication No. 2003-17782, for example, discloses magnetization inversion based on spin-transfer, in which electrons passing through a magnetic material and being spin-polarized are injected into other magnetic materials to cause the magnetization inversion.
Specifically, when spin-polarized electrons passing through a magnetic layer where a magnetization direction is pinned (magnetization pinned layer) enter another magnetic layer where magnetization direction is not pinned (magnetization free layer), spin-transfer torque is given to magnetization of the magnetization free layer. When current of a threshold value or more flows, the magnetization direction of the magnetic layer (magnetization free layer) may be inverted.
For example, if current is applied in the direction perpendicular to a film surface of a great magneto-resistance effect element (GMR element) or of a magnetic tunnel junction element (MTJ element) which includes a magnetization pinned layer and a magnetization free layer, the magnetization direction of at least a part of the magnetic layers of those elements may be inverted.
Accordingly, a memory element including a magnetization pinned layer and a magnetization free layer (memory layer) is formed, in which a polarity of current flowing through the memory element is changed to invert a magnetization direction of the memory layer, thereby rewriting information “0” and information “1”.
A tunnel magneto-resistance effect is used similarly to MRAM by providing a tunnel insulating layer between the magnetization pinned layer and the magnetization free layer (memory layer), thereby reading recorded information.
Magnetization inversion by spin-transfer has an advantage that the magnetization inversion may be realized without increasing an amount of current even though an element is reduced in size.
An absolute value of current flowing through the memory element to cause the magnetization inversion is 1 mA or less in the memory element of about 0.1 μm, for example, and the absolute value is reduced in proportion to a volume of the memory element, which is advantageous in scaling.
Further, since a recording word line that is necessary for MRAM is unnecessary, there is such an advantage that a configuration of a memory cell is simplified.
A memory element using spin-transfer is hereinafter called SpRAM (Spin-transfer Random Access Memory) and spin-polarized current that causes the spin-transfer is called spin injection current.
SpRAM is expected as a nonvolatile memory consuming less electric power and having large capacity while keeping advantages of MRAM that operates at high speed and can be rewritten without a limit of times.
FIG. 1 is a schematic sectional view showing a memory cell in a memory (SpRAM) that uses typical spin-transfer.
A diode or MOS transistor or the like may be used to electrically select a memory cell in order to read information recorded in the memory cell. The memory cell shown in FIG. 1 uses a MOS transistor.
First, a configuration of a memory element 101 forming a memory cell of SpRAM is described.
An anti-ferromagnetic bond is formed between a first magnetization pinned layer 112 and a second magnetization pinned layer 114 through a non-magnetic layer 113. Further, the first magnetization pinned layer 112 is provided in contact with an anti-ferromagnetic layer 111 and has a strong unidirectional magnetic anisotropy caused by exchange interaction between the layers. A pinned layer 102 is configured to have the four layers 111, 112, 113 and 114. Specifically, the pinned layer 102 includes two magnetic layers (first magnetization pinned layer 112 and second magnetization pinned layer 114).
A ferromagnetic layer 116 is configured such that a direction of magnetization M1 is inverted comparatively easily to form a memory layer (magnetization free layer) 103.
A tunnel insulating layer 115 is formed between the second magnetization pinned layer 114 and the ferromagnetic layer 116, specifically, between the pinned layer 102 and the memory layer (magnetization free layer) 103. The tunnel insulating layer 115 disconnects a magnetic bond between the magnetic layers 116 and 114 stacked in a vertical direction and supplies tunnel current. Thus, a TMR (tunnel magneto-resistance) element is configured to have the pinned layer 102 in which the magnetization directions of the magnetic layers are pinned, the tunnel insulating layer 115 and the memory layer (magnetization free layer) 103 in which the magnetization direction can be changed.
Thus, the memory element 101 includes each of the layers 111 to 116 as described above, a ground layer 110 and a topcoat layer 117 to form the TMR element.
A selection MOS transistor 121 is formed in a silicon substrate 120, and a connecting plug 107 is formed on a diffusion layer 123 that is one of diffusion layers provided for the selection MOS transistor 121. The ground layer 110 of the memory element 101 is provided on the connecting plug 107 to be connected thereto. The other diffusion layer 122 of the selection MOS transistor 121 is connected to a sense line through the connecting plug, although not shown in FIG. 1. A gate 106 of the selection MOS transistor 106 is connected to a selective signal line.
The topcoat layer 117 in the memory element 101 is connected to a bit line (BL) 105 provided on top thereof.
In a steady state, magnetization M11 of the first magnetization pinned layer 112 and magnetization M12 of the second magnetization pinned layer 114 are in almost a perfect anti-parallel state based on a strong anti-ferromagnetic bond through the non-magnetic layer 113.
Typically, the first magnetization pinned layer 112 and the second magnetization pinned layer 114 are configured to have equal products of saturation magnetization and film thickness, and therefore a leakage component of a magnetic pole and magnetic field is sufficiently small to be negligible.
A resistance value of TMR element including the layers 114, 115 and 116 is changed depending on whether the direction of magnetization M1 of the ferromagnetic layer 116 that is the memory layer 103 and the direction of magnetization M12 of the second magnetization pinned layer 114 included in the pinned layer 102 are in a parallel state or an anti-parallel state through the tunnel insulating layer 115. The resistance value is low if two of the magnetizations M1, M12 are in the parallel state and the resistance value is high if these are in the anti-parallel state. A whole resistance value of the memory element 101 also changes when the resistance value of TMR element (layers 114, 115, and 116) is changed. Information can be recorded and the recorded information can be read using the above described changes. Specifically, a state where the resistance value is low is assigned to information “0”, for example, and a state where the resistance value is high is assigned to information “1”, thereby binary (1 bit) information being recorded.
In order to rewrite information in the memory cell and to read information recorded in the memory cell, it may be necessary to supply spin injection current Iz. The spin injection current Iz passes through the memory element 101, the diffusion layer 123 and the bit line 105.
A direction of the spin injection current Iz flowing through the memory element 101 may be changed from an upward direction to a downward direction, or vice versa, by changing a polarity of the spin injection current Iz.
Accordingly, information in the memory cell may be rewritten by changing the direction of magnetization M1 of the memory layer 103 in the memory element 101.
Japanese Unexamined Patent Application Publication No. 2005-277147 discloses a configuration of SpRAM in which not only spin injection current is supplied to the memory element, but also a bias current magnetic field is applied to the memory element and other elements, in order to invert magnetization direction of a memory layer in a memory element.
Specifically, for example, in a configuration shown in FIG. 1, spin injection current Iz is supplied to a memory element 101 through a bit line 105, and a bias current magnetic field Hx (not shown) caused by current flowing in the bit line 105 (equal to the spin injection current Iz) is applied to the memory layer 103 in the memory element 101.
Thus, a direction of magnetization M1 of the memory layer 103 can be changed efficiently.
A diagram showing a state of a memory cell is hereinafter called a phase diagram in which a vertical axis represents spin injection current Iz and a horizontal axis represents a bias current magnetic field Hx. Here, the phase diagram is prepared using a peak value of pulse current, in the case of using pulse current as bias current that causes spin injection current Iz and a bias current magnetic field Hx.
FIG. 2 shows an example of an apparatus that measures values for a phase diagram of SpRAM. The apparatus shown in FIG. 2 uses a Helmholtz coil 72 instead of a bit line to generate a bias current magnetic field Hx, and bias current Ib flowing in the Helmholtz coil 72 is supplied independently from an external power supply 71.
The spin injection current Iz flows from or flows out to another driving circuit through the bit line 105 connected to the memory cell.
A direction of magnetization M1 of the ferromagnetic layer 116 that is the memory layer 103 may be changed with the spin injection current Iz and bias current magnetic field Hx.
Using the apparatus shown in FIG. 2, intensity and phase of the spin injection current Iz and bias current magnetic field Hx may optionally be set and values for a phase diagram may be measured.
As described above, in a typical SpRAM, information in the memory cell is rewritten by changing a polarity of the spin injection current Iz. However, there is a case in which a result of magnetization inversion (inverted, or not inverted) may not necessarily be determined with a polarity of the spin injection current alone due to instability in the magnetization inversion phenomenon using spin-transfer.
In such case, in order to securely invert magnetization, an auxiliary bias magnetic field may be needed.
However, when spin injection current Iz and a bias current magnetic field Hx are generated using the same bit line as proposed in Japanese Unexamined Patent Application Publication No. 2005-277147, intensity and phases of the spin injection current Iz and the bias current magnetic field Hx may not be set independently. For example, intensity of the spin injection current and intensity of the bias current may not be adjusted independently and optionally, and timing of the spin injection current, timing for applying the bias magnetic field and a polarity thereof may not be adjusted independently.
Therefore, in a typical SpRAM including a configuration proposed in Japanese Unexamined Patent Application Publication No. 2005-277147, since a condition in the case of rewriting information in a memory cell is restricted, for example, it is difficult to optimize the condition so that electric power consumption may be minimized and the rewriting may be performed at high speed.
Further, instability in the above-described magnetization inversion phenomenon using spin-transfer may not be sufficiently prevented, because the condition in the case of rewriting information in a memory cell is restricted.
Here, FIG. 3A shows the case in which a configuration proposed in Japanese Unexamined Patent Application Publication No. 2005-277147 is applied to a memory cell shown in FIG. 1, and shows each timing of pulse current of spin injection current Iz and of pulse current of bias current Ib that generates a bias current magnetic field.
As shown in FIG. 3A, both of spin injection current Iz and bias current Ib have rectangular pulses in order to simplify an explanation. t0 shows an initial condition; t1 and t2 show the time of the spin injection current Iz and bias current Ib rising respectively; and t3 and t4 show the time of the spin injection current Iz and bias current Ib falling respectively; and ts shows the time at which a finished condition is observed.
Duration of each pulse is t3−t1 for the spin injection current Iz and is t4−t2 for bias current Ib. The spin injection current Iz is switched off before t1, and is switched on at t1, and is switched off at t3.
In such case, part of current flowing through the bit line 105 is used as spin injection current Iz and the other is used as bias current Ib to generate a bias current magnetic field Hx. Therefore, the spin injection current Iz and the bias current Ib are supplied to the bit line 105 from the same driving power supply, and so the injection current Iz and the bias current Ib may not be applied at a different timing.
Consequently, time t1 of rising 91 in a pulse of the spin injection current Iz and time t2 of rising 92 in a pulse of the bias current Ib will surely be the same time.
Subsequently, FIGS. 3B and 3C show examples of change in electric resistance of the memory element 101 over time when a typical SpRAM is used. Two curves in FIGS. 3B and 3C correspond to spin injection current Iz ±2.5 mA that exceeds a threshold value for inverting a magnetization direction, respectively. Here, duration (t3−t1 in FIG. 3A) for a pulse of the spin injection current Iz is 5 ns (nanoseconds) and a peak value of a pulse of the bias current Ib is zero. Also, t5−t1 in FIG. 3A is 10 ns.
FIG. 3B shows an example in which an initial resistance is started from a low resistance state (“0” state) and a magnetization direction can be normally inverted.
As shown in FIG. 3B, a high resistance state inverted from the initial state (a low resistance state) can be obtained under a condition where a peak value of spin injection current Iz is −2.5 mA, and a low resistance state remains unchanged as the initial state under a condition where a peak value of spin injection current Iz is +2.5 mA.
On the other hand, FIG. 3C shows an example in which an initial resistance is started from a high resistance state (state “1”) and magnetization direction may not be inverted.
As shown in FIG. 3C, a low resistance state inverted from an initial state is temporarily obtained under a condition where a peak value of spin injection current Iz is +2.5 mA; however, the resistance state returns to the original high resistance state when the spin injection current Iz is turned off after passing 5 ns, and a high resistance state remains unchanged as the initial state under a condition where a peak value of spin injection current Iz is −2.5 mA.
A phenomenon in which switching from a high resistance as an initial resistance shown in FIG. 3C may not be inverted normally is observed in the following cases. Specifically, in the case where magnetization M1 of the memory layer (magnetization free layer) 103 does not reach a parallel state due to short duration for spin injection current Iz, in the case where an inverse magnetic domain is generated in a part of the magnetization free layer 103 in a switching process where a magnetization direction changes, or in the case where magnetization M11 or M12 of the pinned layer 102 that may not change basically moves a little by huge spin torque.
Spin torque tends to increase along a current magnetic field in spiral shape formed by the spin injection current Iz, and therefore an inverse magnetic domain of a pattern that resists the current magnetic field in spiral shape formed by the spin injection current Iz is formed in a magnetization free layer 103.
SpRAM is an excellent memory in which current (inversion threshold current) necessary for inverting a magnetization direction of a memory layer can be reduced using spin torque, and intensity of spin torque is huge that easily exceeds torque caused by a static magnetic field which increases in inverse proportion to the size of an element.
Thus, SpRAM has a characteristic that if the size of an element is small, it is advantageous to obtain more inversion threshold current; however, the huge spin torque may cause instability in a spin-transfer magnetization inversion phenomenon. With such instability, a phenomenon in which a magnetization direction may not be inverted by a polarity of the spin injection current alone is observed, as shown in FIG. 3C.
Next, a relationship between the above-described phenomenon and a phase diagram is explained.
A typical phase diagram includes: a hysteresis area 80; an area 81 where a memory cell is in “0” state (low resistance state) regardless of an initial magnetization state; an area 82 where a memory cell is in “1” state (high resistance state) regardless of an initial magnetization state; and an unstable operation area 83 where the above-described three areas coexist.
In order to function as a memory in which SpRAM has a realistic margin (operating margin), three areas (hysteresis area 80, “0” state area 81 and “1” state area 82) may need to independently exist as sufficiently wide areas respectively.
As shown in FIG. 3C, a phenomenon in which a magnetization direction may not normally be inverted by a polarity of spin injection current Iz alone appears on a phase diagram as an unstable operation area 83 where two or more states coexist in the “0” state area 81 and in the “1” state area 82.
FIG. 4 shows an example of a measured phase diagram of a typical SpRAM in which duration of spin injection current Iz and that of bias current Ib are 5 ns.
The phase diagram shown in FIG. 4 is a diagram showing a state of a memory cell in a switching finished condition (for example, t5 in FIG. 3A) with a peak value of a pulse of spin injection current Iz as a vertical axis and a peak value of a pulse of a bias current magnetic field Hx as a horizontal axis.
As shown in FIG. 4, the unstable operation area 83 where the three states 80, 81, 82 coexist appears upper right in the figure (first quadrant) and lower left in the figure (third quadrant).
It should be noted that the “0” state area 81 appears on the second quadrant, the “1” state area 82 appears on the fourth quadrant and the unstable operation area 83 appears on the first and third quadrants in FIG. 4, however, these are not necessarily universal characteristics. Depending on a method of defining the direction of spin injection current Iz and the directions of magnetization M11 and magnetization M12 of the pinned layer 102, the “0” state area 81, the “1” state area 82 and the unstable operation area 83 may appear on different quadrants from those shown in FIG. 4.
In the case where the unstable operation area 83 appears in the phase diagram as shown in FIG. 4, spin injection current Iz and bias current Ib when performing magnetization inversion may need to be set to the outside of the unstable operation area 83.
However, it may be difficult to set current so as not to be in the unstable operation area 83 in such a configuration that the currents Iz, Ib are supplied from the same bit line.